Designing the whole chip at once
Ricursive Intelligence is betting that the bottleneck in artificial intelligence is no longer only the number of data centres but the speed at which chips can be designed. Founders Anna Goldie and Azalia Mirhoseini presented the idea at TechCrunch Disrupt, describing a system that designs chips, learns from each iteration and applies what it learned to the next one.
Goldie said demand for compute could grow at least 10,000-fold over five years. Building 10,000 times more data centres is not realistic, she argued, so the industry has to make chips that use bandwidth, wafers and fab capacity more efficiently.
Odd shapes that work
Instead of splitting a chip into dozens of smaller blocks and optimising each one, Ricursive optimises the whole device. The founders say that freedom lets the software find layouts engineers would not try by hand. AlphaChip, the system they developed earlier, produced a circular, donut-shaped arrangement of components that surprised engineers and then outperformed conventional layouts.
They said the same approach can produce wave-like patterns and other structures they plan to describe later. The argument is that human designers bring the ideas and constraints, while the machine handles placement and routing at a scale no team can match manually.
Custom silicon for narrow markets
If a new chip takes a year or two to design, companies must be highly selective about which ones they build. If design time falls to about a week, custom chips become affordable for smaller markets: space hardware, augmented and virtual reality headsets, and experimental biological computing.
The company has not published benchmark data or customer commitments, and independent checks of its claims are not yet possible. The wider industry is moving in the same direction. Chipmakers and cloud providers are already using machine learning to place components and tune manufacturing, and several design tools now include AI assistants.
What remains open is whether AI-designed chips can be manufactured at high yield in advanced process nodes, where physics and lithography limit how creative a layout can be. For now, the pitch is straightforward: less waste per wafer, less power per operation, and design cycles short enough that specialised chips make financial sense.
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